Issues and Solutions of the Modern Semiconductor IC Technology

Project Description
EE463 Semiconductor IC Technology Semester-End Homework

Q1. As the device scaling continues, the conventional SiO2 was replaced with high-K dielectric materials for the gate dielectric material. Discuss (1) the limitations of SiO2 and the reason for the use of high-K dielectrics, (2) issues on deposition process of high-K dielectrics, (3) problems of high-K dielectrics, and (4) the methods to overcome the problems of high-K dielectrics.

Q2. As for the design rule goes smaller than 32 nm, CMOS transistor structure was shift from conventional 2D planar structure to 3D FINFET structure. (1) Explain the fabrication process flow of 3D FINFET structure with the help of drawings, (2) In case of source/drain doping of 3D FINFET structure, ion implantation has problems of shadow effect. Discuss the methods to overcome the problem.

Q3. One of the ways to enhance drain current is to enhance carrier (electron and hole) mobility. A lot of researches have been made to enhance carrier mobility. Discuss at least more than three ways to enhance the carrier mobility as detail as possible, and also the problems that can newly occur because of the use of the new mobility enhancement techniques.

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