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TMC: Temperature Management on CIS using chopper
Note: The details cannot be disclosed here due to confidentiality concerns This project is conducted by studying various offset techniques such as trimming, auto-zeroing, and chop...
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ABBG: Adaptive Body Bias Generator in CIS
In SoC, more and more Logic Gate is required according to Moore's law, and accordingly, the power consumption also increases. The heat generated in high...
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JSSC Paper Study: Rail-to-Rail Op-Amp by Hogervost(1994)
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DBR: Doubler of CIS
In a CIS circuit, a Doubler is a block that produces a clear voltage of 4.5V, which is about twice as high as the nominal voltage of 2.5V. The most main...
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Ramp: Single Slope ADC
Basically, CIS utilizes the Column-parallel ADC Architecture, which processes data with one long ADC per column. Unlike a typical layout, the CIS layout...